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Filtronic
Solid State
FEATURES
DRAIN PAD (x4)
LP3000/LPV3000
2W Power PHEMT
* * * * *
+33.5 dBm Typical Power at 18 GHz 7 dB Typical Power Gain at 18 GHz +30.5 dBm at 3.3V Battery Voltage Low Intermodulation Distortion 45% Power-Added-Efficiency at 18 GHz
SOURCE BOND PAD (x2)
GATE PAD (x4)
DIE SIZE: 28.3 x 16.5 mils (720 x 420 m) DIE THICKNESS: 2.6 mils (65 m typ.) BONDING PADS: 1.9 x 2.4 mils (50 x 60 m typ.)
DESCRIPTION AND APPLICATIONS
The LP3000 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-write 0.25 m by 3000 m Schottky barrier gate. The recessed "mushroom" gate structure minimizes parasitic gate-source and gate resistances. The epitaxial structure and processing have been optimized for reliable high-power applications. The LP3000 also features Si3N4 passivation and is available with plated source via-holes (LPV 3000) as an option for improved high-frequency performance. Also available in a ceramic flanged package (P100) and ball grid array package. Typical applications include commercial and military high-performance power amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. The LPV 3000/LP 3000 may be procured in a variety of grades, depending upon specific user requirements. Standard lot screening is patterned after MIL-STD-19500, JANC grade. Space-level screening to FSS JANS grade is also available.
PERFORMANCE SPECIFICATIONS (TA = 25C)
SYMBOLS IDSS P1dB G1dB ADD IMAX GM VP IGSO BVGS BVGD J PARAMETERS Saturated Drain-Source Current VDS = 2V VGS = 0V Output Power at 1dB Gain Compression f = 18 GHz VDS = 8.0V, IDS = 50% IDSS (LP. LPV) Power Gain at 1dB Gain Compression f = 18 GHz VDS = 8.0V, IDS = 50% IDSS (LP) f = 18 GHz VDS = 8.0V, IDS = 50% IDSS (LPV) Power-Added Efficiency (typ. for Class A operation) Maximum Drain-Source Current VDS = 2V VGS = +1V Transconductance VDS = 2V VGS = 0V Pinch-Off Voltage VDS = 2V IDS = 10mA Gate-Source Leakage Current VGS = -5V Gate-Source Breakdown Voltage IGS = 15mA Gate-Drain Breakdown Voltage IGD = 15mA Thermal Resistivity MIN 800 TYP 1060 MAX 1100 UNITS mA
33.0 4.0 6.0
33.5 6.0 7.0 45 1700 900 -1.2 15 -15 -16 20
dBm dB dB % mA mS V A V V C/W
725 -0.25 -12 -12
-2.0 125
Get Curtice Model DSS-027 WG Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950
Filtronic
Solid State
ABSOLUTE MAXIMUM RATINGS (25C) 1 SYMBOL PARAMETER RATING VDS Drain-Source Voltage 12V VGS Gate-Source Voltage -5V IDS Drain-Source Current 2 x IDSS IG Gate Current 120 mA PIN RF Input Power 1.2 W TCH Channel Temperature 175C TSTG Storage Temperature -65/175C 3,4 PT Power Dissipation 6.0W
LP3000/LPV3000
2W Power PHEMT
RECOMMENDED CONTINUOUS OPERATING LIMITS 2 SYMBOL PARAMETER RATING VDS Drain-Source Voltage 8V VGS Gate-Source Voltage -1V IDS Drain-Source Current 0.8 x IDSS IG Gate Current 40 mA PIN RF Input Power 600 mW TCH Channel Temperature 150C TSTG Storage Temperature -20/50C 3,4 PT Power Dissipation 5.0 W GXdB Gain Compression 8 dB
NOTES: 1. Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. 2. Recommended Continuous Operating Limits should be observed for reliable device operation. 3. Power Dissipation defined as: PT (PDC + PIN) - POUT, where: PDC = DC bias power, POUT = RF output power, and PIN = RF input power. PT(W) 4. Power Dissipation to be de-rated as follows: 5. Specifications subject to change without notice. 6.0 -40 mW/C Example #1 : VDS = 8V, IDS = 535 mA 5.0 PIN = POUT = 0 dBm (quiescent condition): PT = PDC = 4.28W -40 mW/C Max. continuous T HS = 25C Example #2: VDS = 8V, IDS = 535 mA PIN = 26.5 dBm POUT = 33.5 dBm PT = (4.28+0.45) - 2.24 = 2.49W Max. continuous T HS = 88C 150 175 25 THS(C) HANDLING PRECAUTIONS: PHEMT chips should be stored in a dry nitrogen environment until assembly. Care should be exercised during handling to avoid damage to the devices. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A (0-500V), and further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. ASSEMBLY INSTRUCTIONS: The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280290C; maximum time at temperature is 1 min. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260C. APPLICATIONS NOTES AND DESIGN DATA: Applications Notes are available from your local FSS Sales Representative, or directly from the factory. Complete design data, including S-parameters, Noise data, and Large-Signal models, is available on 3.5" diskette, or may be down-loaded from our Web Page.
Get Curtice Model DSS-027 WG Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950

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